Capability Hardware Enhanced RISC Instructions

CHERI (Capability Hardware Enhanced RISC Instructions) is a joint research and development project of SRI International, the University of Cambridge, UKRI and Capabilities Limited to revisit fundamental design choices in hardware and software to improve system security dramatically.

CHERI has been supported by the DARPA CRASH, MRC, and SSITH programs since 2010, as well as other DARPA research and transition funding. Since 2019, the development of Arm's experimental CHERI-enabled Morello processor, SoC, and the board has been supported by UKRI. We gratefully acknowledge DARPA, UKRI, and our other supporters, including EPSRC, ERC, Google, and Arm.

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Below you can view a video that has a brief introduction to CHERI and the Morello Board.